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Avnet Electronics Marketing offers the Zynq-7000 All Programmable SoC/Analog Devices Intelligent Drives Kit for Motor Co...
via embedded-computing

Avnet Electronics Marketing, an operating group of Avnet, Inc. (NYSE:AVT), today announced the Zynq®-7000 All Programmable SoC/Analog Devices Intelligent Drives Kit for prototyping next-generation motor control applications. Combining the Xilinx...
(IND) SENIOR SOFTWARE ENGINEER - SYSTEM SIMULATION METHODOLOGY
via yeswecan.co.in

Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable...
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Xilinx Vivado: Beginners Course to FPGA Development in VHDL Udemy
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Course Description Course Update: Note! This course price will increase to $60 as of 1st December 2016 from $50. The price will increase regularly due to new updated Lectures and Content. Get this course while it is still low. Course Content Updated...

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TSU input clock

When trying to build the Processor Subsytem attached I get a critical warning related to the TSU input clock. CRITICAL WARNING: [BD 17-148] Frequency mismatch between port /ps_SUBSYS/zynq_ultra_ps_e_0/EMIO_ENET_TSU_CLK : 144 and user selected paraameter...
Partial Reconfiguration with 2 PCIe cores for XCKU-085

Is it possible to support Partial Reconfiguration on XCKU-085 with 2 PCIe cores? If not, what alternative options are available?
[AXI INTERCONNECT] Understanding AXI arbritration

Hi, In my design i've got an external memory which can be read and write by the PS or by the PCIe link. Each of this master is connected to an AXI interconnect which connected to others IP and the memory controller. But i've got some issues when the...
Replacement for XCF32PFS48C

Hello there, I'm looking for a drop in replacement for this Config PROM interface with a Spartan-6. FPGA. Any advice? Thank you!
Using OOC synthesis in Ultrascale+ RFSOC

Reading manual for hierarchical design (UG905) wa have noted that this design method it's not appliacable for Ultrascale+ family devices. It's meaning that OOC synthesys it's not possible for this devices ? Only Global Syntehsys is allowed ?

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AMD Customer Community

Hi: I am bringing up a ZCU19EG board. Currently, the configuration is set such that the boot-mode is QSPI. Kernel is taken from SD card. Everything was working fine. However, about a couple of days ag...
AMD Customer Community

Discuss Processor system design for Zynq UltraScale+ MPSoC/RFSoC, Zynq-7000, MicroBlaze, and PicoBlaze. Includes both Processor Subsystem (PS) peripherals and Programable Logic (PL) IP Peripherals tha...